Hardware Security IPs Architected For Your SoC

End-to-end IoT device security, from chip to cloud. We combine silicon IP and software to give every device an unclonable identity rooted in quantum-driven entropy.

Inside you'll find:

How Siemens EDA uses our security IP to enable secure Design-for-Test (DFT)
Secure access control over the JTAG/IJTAG network — lock/unlock and authenticate test data
Production-ready secure DFT in weeks, with no custom root-of-trust build

Who We Are

Security Built Into the Silicon Itself

Crypto Quantique secures silicon across the product lifecycle — from chip design and manufacture, through provisioning, to in-field management. We pair customisable silicon IP with expert guidance, so SoC integrators and embedded teams can make security decisions with confidence.

Product Portfolio

One Composable Security Portfolio

Hardware root of trust, PUF-based identity, entropy, cryptographic acceleration and attack detection — composable into a security architecture sized to the device.

Low-area, low-power IP, right-sized around your boot flow, memory architecture, trust boundaries and gate-count constraints.

Backed by expert guidance on system-level trade-offs, from security architecture through to tape-out.

QDID™ Quantum PUF

A quantum entropy-source PUF that harnesses quantum-tunnelling current in standard silicon, with an integrated quantum TRNG. Multiple internally generated, unclonable device identities — no key injection, no HSM.

QRoot™ Root of Trust

A compact hardware root of trust for resource-constrained MCUs and IoT, enabling measured boot, attestation and sealed storage — plus the QRoot™ Agile Secure Element for richer SoC designs.

Post-Quantum Cryptography

Hardware accelerators for the NIST PQC standards — ML-KEM (Kyber), ML-DSA (Dilithium) and SLH-DSA (SPHINCS+) — to keep devices secure against the coming wave of quantum attacks.

Cryptographic Cores

Lightweight, silicon-proven AES, Ascon, SHA-2/3 and elliptic-curve (ECC/ECDH) cores, area-optimised and available with side-channel and fault-injection protection.

True Random Number Generators

Two entropy sources — an all-digital TRNG and a quantum QTRNG — delivering high-quality, standards-validated randomness for keys, nonces and initialization vectors.

Attack Detection

Silicon-validated side-channel and fault-injection detectors that catch voltage and clock glitch attacks, raising latched status flags for system-level countermeasures.

Download the full IP brochure

Case Study

Crypto Quantique & Siemens EDA

We've recently partnered with Siemens EDA, who are using our security IP to enable secure Design-for-Test (DFT).

We help DFT, ATE and product-management teams maximise silicon reliability and uptime while reducing total cost of ownership.

Secure DFT & Product Lifecycle Management

A comprehensive solution to lock/unlock test structures and authenticate/encrypt test data.

Full secure access control over the JTAG/IJTAG network.

EDA automation, including seamless integration with the test solution based on user-defined configuration.

Eliminates the need to integrate a complex root of trust (RoT) for the functional mode of operation.

Scalable with increasing design sizes and heterogeneous packaging needs.

Secure remote access to test logics and embedded analytics.

Net result: production-ready secure DFT integrated in weeks — no custom root-of-trust build, no multi-month integration.

Evaluate

Get the Full Portfolio in One Brochure

Every Crypto Quantique silicon IP — root of trust, quantum PUF identity, PQC and cryptographic cores — in a single overview, available in English and Korean.